Conventional counters typically only count one type of edge (rising or falling) of the input signal, and cannot achieve a 50/50 duty cycle output when the divide ratio is odd. Most conventional counter designs, an example of which is depicted in FIG. 6, use flip-flop cells together with combinational feedback logic and have a long latency delay, generally a three-gate delay minimum (where a D flip-flop is considered to incur a two-gate delay). In addition, multiple gate paths, usually resulting from a logical OR function combining two signal paths, result in asymmetrical responses on positive and negative events. Conventional designs also have a high AND/OR logic gate count, with the example in FIGURE X having 27 (six AND/OR gates in each of the four D flip-flop).
There is, therefore, a need in the art for an edge counter with minimal gate delay, and preferably with a single gate path and low logic gate count.